The present invention relates to a semiconductor memory device, especially a circuit of generating internal voltages used for internal operations of a semiconductor memory device, and more particularly, to a semiconductor memory device that operates with low power by reducing a current consumed in generating an internal voltage.
Most of semiconductor devices such as DRAMs include an internal voltage generating circuit configured to generate a plurality of internal voltages having various voltage levels by the use of a power supply voltage (VDD) and a ground voltage (VSS) supplied from the outside. Therefore, a semiconductor device supplies a plurality of internal voltages required for operation of a circuitry inside a chip by itself through the internal voltage generating circuit.
In general, a process of generating the plurality of internal voltages includes a process of generating a reference voltage having a reference voltage level, and a process of generating an internal voltage through a charge-pumping or down-converting method using the generated reference voltage.
Examples of the internal voltage generated through the charge-pumping method are a boosted voltage (VPP) and a back bias voltage (VBB). Examples of the internal voltage generated through the down-converting operation are a core voltage (VCORE), and the like.
The boosted voltage (VPP), which has a higher voltage level than an external power supply voltage (VDD), is supplied to a word line connected to a gate of a cell transistor when a cell is accessed, thereby preventing the loss of cell data caused by a threshold voltage (Vth) of the cell transistor.
The back bias voltage (VBB), which has a lower voltage level than a ground voltage (VSS), reduces a variation in the threshold voltage (Vth) of the cell transistor due to the body effect on the cell transistor. Resultingly, the back bias voltage (VBB) increases the reliability of operation of the cell transistor, and reduces a channel leakage current generated in the cell transistor.
The core voltage (VCORE), which has a lower voltage level than the external power supply voltage (VDD) and a higher voltage level than the ground voltage (VSS), reduces a power required for maintaining a voltage level of data stored in a cell and also allows the cell transistor to be stably operated.
The internal voltage generator of generating the internal voltages, i.e., VPP, VBB and VCORE, is designed such that it operates to have a predetermined variance within an operating voltage region and an operating temperature range of a semiconductor memory device.
FIG. 1 is a block diagram of an internal voltage generating circuit in a conventional semiconductor memory device.
Referring to FIG. 1, the internal voltage generating circuit in the conventional semiconductor memory device includes an enable signal generator 100, a reference voltage generator 140, and a plurality of internal voltage generators 120A, 120B, 120C, 120D and 120E. The enable signal generator 100 generates an enable signal CTRL of which an activation timing is determined in response to activation of an active command ACT corresponding to operation of the semiconductor memory device. The enable signal CTRL is deactivated after a predetermined time from a deactivation timing of the active command ACT. The reference voltage generator 140 generates a reference voltage VREF having a constant level regardless of process, voltage and temperature (PVT) variations. The plurality of internal voltage generators, i.e., zeroth to fourth internal voltage generators 120A, 120B, 120C, 120D and 120E generate internal voltages VINT based on a predetermined target level corresponding to the reference voltage VREF, and are turned on/off in response to the enable signal CTRL.
The first internal voltage generator 120A includes a zeroth internal voltage detecting unit 122A, and a zeroth voltage driving unit 124A. The zeroth internal voltage detecting unit 122A detects an internal voltage terminal (hereinafter, referred to as VINT terminal) based on the predetermined target level corresponding to the reference voltage VREF, and is turned on/off in response to the enable signal CTRL. The zeroth voltage driving unit 124A drives the VINT terminal to a voltage level corresponding to the predetermined target level in response to an output signal VINT_DET0 of the zeroth internal voltage detector 122A. Likewise, the first internal generator 120B includes a first internal voltage detecting unit 122B and a first voltage driving unit 124B, the second internal generator 120C includes a second internal voltage detecting unit 122C and a second voltage driving unit 124C, the third internal generator 120D includes a third internal voltage detecting unit 122D and a third voltage driving unit 124D, and the fourth internal generator 120E includes a fourth internal voltage detecting unit 122E and a fourth voltage driving unit 124E. The first to fourth internal voltage detecting units 122B, 122C, 122D and 122E operate in the same manner as the zeroth internal voltage detecting unit 122A, and thus further description for them will be omitted herein. Similarly, first to fourth voltage driving units 124B, 124C, 124D and 124E operate in the same manner as the zeroth voltage driving unit 124A, and thus further description for them will also be omitted herein.
The internal voltages VINT generated through the plurality of internal voltage generators 120A, 120B, 120C, 120D and 120E are input to an internal circuit 160 of the semiconductor memory device and then used to perform predetermined internal operations.
FIG. 2 is a circuit diagram of the enable signal generator 100 of the internal voltage generating circuit in the conventional semiconductor memory device in FIG. 1.
Referring to FIG. 2, the enable signal generator 100 includes a first inverter INT1 configured to receive an active command ACT to output an output signal D1, a delay element configured to delay the active command ACT by a predetermined delay time, a second inverter INT2 configured to receive an output signal of the delay element to output an output signal D2, and a NAND gate NAND configured to perform a NAND operation on the output signals D1 and D2 of the first and second inverters INT1 and INT2 to output the enable signal CTRL.
Operation of the internal voltage generating circuit in the conventional semiconductor memory device will be described below.
FIG. 3 is a timing diagram of input/output signals of the enable signal generator 100 in FIG. 1.
Referring to FIG. 3, the enable signal generator 100 deactivates the output signal D1 of the first inverter INT1 in response to activation of the active command ACT ({circle around (1)}).
The enable signal CTRL is activated in response to deactivation of the output signal D1 of the first inverter INT1 ({circle around (2)}).
After a predetermined time from the deactivation timing of the output signal D1 of the first inverter INT1, the output signal D2 of the second inverter INT2 is deactivated ({circle around (3)}).
Thereafter, the output signal D1 of the first inverter INT1 is activated in response to the deactivation of the active command ACT ({circle around (4)}), but the output signal D2 of the second inverter INT maintains its deactivation state. Hence, the enable signal CTRL is still at the activation state.
The output signal D2 of the second inverter INT2 is activated after a predetermined time from the activation timing of the output signal D1 of the first inverter INT1 ({circle around (5)}), and then the enable signal CTRL is deactivated in response to activation of the output signal D2 of the second inverter INT2 ({circle around (6)}).
That is, the conventional enable signal generator 100 generates the enable signal CTRL having an activation period that is longer than the activation period of the active command ACT by the predetermined delay time.
In general, the activation timing of the active command ACT means a timing when data input/output (I/O) operation starts to be performed in the semiconductor memory device.
Although not shown, there is a precharge command (PCG) that is counter to the active command ACT. That is, the precharge command (PCG) is deactivated when the active command ACT is activated; however, the precharge command (PCG) is activated when the active command ACT is deactivated.
Therefore, the activation timing of the precharge command PCG is a timing when the data I/O operation is finished in the semiconductor memory device because the activation timing of the active command ACT is the input/output timings of the data.
In the conventional enable signal generator 100, however, although the enable signal CTRL is activated in response to the active command ACT, the enable signal CTRL is not deactivated directly in response to deactivation of the active command ACT but deactivated after a predetermined time from the deactivation timing of the active command ACT.
Here, the enable signal CTRL controls the generation of the internal voltage VINT by controlling the internal voltage generators 122A, 122B, 122C, 122D and 122E to be turned on/off.
Therefore, when the enable signal CTRL is activated, all the plurality of internal voltage generators 122A, 122B, 122C, 122D and 122E are enabled to increase a voltage level of the VINT terminal. On the contrary, when the enable signal CTRL is deactivated, all the plurality of internal voltage generators 122A, 122B, 122C, 122D and 122E are disabled to decrease a voltage level of the VINT terminal.
That is, it is no wonder that the semiconductor memory device normally performs the data I/O operation by generating the internal voltage VINT during the activation period of the active command ACT.
However, it is not proper that the internal voltage generating circuit still generates the internal voltage VINT even after the active command ACT is deactivated and the precharge command (PCG) is activated, that is, even after the data I/O operation has been finished in the semiconductor memory device.
Why the conventional internal voltage generating circuit generates the internal voltage VINT for a predetermined time even after the active command ACT is deactivated is because the internal voltage VINT is mainly used to input/output data, and further small amount of the internal voltage VINT is also necessarily used in order for the semiconductor memory device to return to an initial state before the data I/O operation was performed, in response to the precharge command (PCG) after the data I/O operation is finished.
For example, if the operation of increasing a voltage level of the VINT terminal is promptly terminated soon after the data I/O operation is finished in a state that the voltage level of the VINT terminal is lower than the predetermined level due to the data I/O operation, data may not be input/output normally during a next data I/O operation. Accordingly, the internal voltage VINT must be generated for a predetermined time in order that the semiconductor memory device may return to the initial state even after the data I/O operation is finished.
For this reason, the conventional semiconductor memory device has a configuration such that it does not generate the internal voltage VINT directly in response to the active command ACT but generates the internal voltage VINT using the enable signal CTRL. However, such a configuration leads to several problems below.
The internal voltage generating circuit of FIG. 1 includes the plurality of internal voltage generates 120A, 120B, 120C, 120D and 120E to drive the VINT terminal in parallel. Therefore, the internal voltage (VINT) generating circuit is designed to have a relatively small occupation area in the semiconductor memory device and to have a relatively high driving force.
If all the plurality of internal voltage generates 120A, 120B, 120C, 120D and 120E are enabled even in the case where the semiconductor memory device uses a great amount of the internal voltage VINT, the semiconductor memory device has a driving force enough to normally operate the semiconductor memory device. That is, when all the plurality of internal voltage generates 120A, 120B, 120C, 120D and 120E are enabled, the driving force becomes relatively very high. In this case, a great amount of current is also consumed.
However, in a period when the active command ACT is deactivated and the precharge command (PCG) is activated, the data I/O operation has been finished, and thus the amount of the internal voltage VINT to be used in this period is relatively small.
Nevertheless, the conventional semiconductor memory device generates the internal voltage VINT with the maximum driving force by enabling all the plurality of internal voltage generates 120A, 120B, 120C, 120D and 120E for a predetermined time. That is, the conventional semiconductor memory device generates the internal voltage VINT with a high driving force although it is unnecessary to use the high driving force.
Since the driving force is proportional to the current consumption, such a high driving force causes a great amount of current to be unnecessarily consumed. Of course, it is possible to somewhat reduce the current consumption by appropriately controlling a predetermined time required to generate the internal voltage VINT additionally, but a current still consumed unnecessarily even in this case.